1. Technical Field
The invention relates to a control circuit for a switching regulator and a method for regulating electrical signal, and more particularly, the invention relates to a control circuit and a method for regulating electrical signal capable of allowing the switching regulator to maintain ultra low current consumption in a sleep mode.
2. Description of Related Art
In modern times, circuit systems often require a voltage regulator for providing an accurate output voltage to serve as a basis for the operation of other circuits. In many cases, switching regulators may self-generate one reference voltage, and then adjust aforesaid output voltage by utilizing an error amplifier and a feedback mechanism.
FIG. 1 is a schematic block diagram of a switching regulator according to the conventional technology. Referring to FIG. 1, a switching regulator 100 includes a regulator circuit 120, a clock generator 140, a feedback control circuit 150 and a sleep control unit 160. This conventional switching regulator is capable of regulating the output voltage according to a reference voltage VREF and a feedback voltage VFB. The regulator circuit 120 is configured to receive a driving signal in order to stabilize the output voltage within a predetermined electrical potential range. The clock generator 140 provides a clock signal OSC and a control signal ENH. The feedback control circuit 150 provides a feedback control mechanism according to the feedback voltage VFB and the reference voltage VREF.
FIG. 2 illustrates a signal waveform diagram of the switching regulator according to the conventional technology. When the switching regulator of FIG. 1 is in a no-load state or a light-load state, the switching regulator enters a sleep mode. Architecture of the sleep control unit 160 is configured to confine an upper limit (VH) and a lower limit (VL) of the feedback voltage VFB. As illustrated in FIG. 2, when VFB is greater than VH, in a latch (not illustrated) inside the sleep control circuit 160, a set terminal SET is equal to 1 and a reset terminal RESET is equal to 0. Accordingly, an output terminal Q1B of the latch is also equal to 0 (Q1B=0). In this case, a number of times for switching the clock signal OSC is reduced (OSC is converted into an OSC skip period). When the feedback voltage VFB is less than VL, in the latch, the set terminal SET is equal to 0, the reset terminal RESET is equal to 1, and the output terminal is also equal to 1 (Q1B=1=the control signal ENH). In this case, the clock signal OSC is normally switched. However, when the feedback voltage VFB falls between the upper limit and the lower limit (VL<VFB<VH), the output terminal Q1B is equal to the control signal (Q1B=ENH) and maintained at the previous state. Therefore, although this architecture is capable of reducing a current consumption, if an initial value of the feedback voltage VFB falls between the upper limit and the lower limit (VL<VFB<VH) when the switching regulator is switched from a normal mode to the sleep mode, the output terminal Q1B of the latch will still be maintained at the previous state. Accordingly, the control signal ENH is equal to Q1B so ENH and Q1B are both maintained to be 1, such that the switching regulator may constantly maintain in the normal mode and fail to dynamically adjust the current consumption.
Thus, in the conventional switching regulator, when the system enters the sleep mode, a specific amount of the current consumption may still exist at the output terminal of the switching regulator (e.g., the current consumption of each component in the switching regulator may still exist). As a result, in case of applications in batteries or portable electronic devices, a power supply of such system cannot satisfy market demands for low current consumption and longer battery usage time.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.